Phase locked loops (PLLs) have a variety of applications in various fields. In hard disc drives, for example, PLLs are commonly used to extract clock information from the data signal and thus synchronize the data retrieval with internal functions of the read channel, to ensure that incoming data is retrieved and analyzed correctly. In order to perform this function, a PLL needs to be able to follow the phase as well as the frequency of the read signal. A key component of PLLs is the phase measure circuit, which is also referred to as a phase comparator or phase detector in the literature.
FIG. 1 is a block diagram of an analog phase-locked loop. The input to the phase locked loop is reference frequency 102, which is fed into phase detector 104. The other input to the phase detector will be discussed below. The output of phase detector 104 is fed into charge pump 106. (It should be noted that many, but not all PLLs include charge pumps; some simply couple the phase detector directly to the low-pass filter.) The charge pump creates a current for the period of time during which the phase error exists. This signal is filtered through low-pass filter 108 to obtain a voltage Vc, which is fed into voltage controlled oscillator (VCO) 114. Low-pass filter 108 is made up of a resistor 110 and capacitor 112 together in series, but placed in shunt with the output of charge pump 106. Various higher-order filters may be used, but low-pass filter 108, as depicted, provides the basic building block for higher order filters. The significance of low-pass filter 108's structure will be discussed shortly.
VCO 114's output (node 116) is the frequency output from the circuit and equals N*f(ref. This signal is fed into frequency divider 118 that divides f(clk) by N, which is an integer value in the range of 1, 2, . . . , N. The output of frequency divider 118 equals f(clk)/N at steady-state and this is the second input to phase detector 104. This completes the feedback loop. Since both inputs to phase detector 104 equal f(clk)/N, any shift in one of these frequencies will be detected by phase detector 104 and feed through charge pump 106 to voltage controlled oscillator 114. This results in f(clk) being adjusted to bring it back into sync to a value N*f(ref). This in sync condition is known as being “in lock,” hence the name phase-locked loop.
At steady-state, as one skilled in the art will recognize, the voltage Vc will be a DC constant. For instance, when a PLL is used as a frequency synthesizer, Vc will largely stay constant. The low-pass filter of a PLL is therefore designed to block out spurious AC signals that may corrupt Vc.
In many cases, however, the reference voltage will vary over time. One commonly encountered situation where this occurs is when a PLL is used to demodulate frequency-modulated (FM) radio signals. In an FM radio signal, the frequency of the signal is constantly changing. Thus, there is a need to be able to rapidly re-obtain lock.
The structure of low-pass filter 108 addresses these dual concerns. Capacitor 112 drains away high-frequency signal components to ground, thus spurious AC signals are prevented from reaching VCO 114. Capacitor 112 by itself, however, makes for a rather unstable system, and particularly so because it is coupled to charge pump 106. Instantaneous changes in the reference frequency can result in ringing at a lone shunt capacitor. This translates into a slower lock, since the ringing must die down before a stable lock is established. Thus, resistor 110 is placed in series with capacitor 112 to provide a damping effect. This damping reduces the degree and length of ringing, so that lock may be more rapidly obtained.
In order to fully implement a PLL in an ASIC (application-specific integrated circuit) design using programmable circuit arrays such as FPGAs (field programmable gate arrays), a fully digital PLL design is needed, and analog circuit components such as phase/frequency detector 104 must be replaced with equivalent digital circuits. An example of an existing approach to the design of an all-digital phase/frequency detector can be found in U.S. Pat. No. 5,757,868 to Kelton et al. A schematic diagram of the Kelton et al. phase/frequency detector is provided in FIG. 2.
In the Kelton et al. phase/frequency detector, an input signal 208 is synchronized at D flip-flop 201 with a reference clock signal 200 provided by local oscillator 203. Reference clock signal 200 is at a frequency that is 2N times a base reference frequency LO, where N is a constant. Output 209 of D flip-flop 201 is combined with a second reference clock signal 212 at exclusive-nor (XNOR) gate 202. Reference clock signal 212 is at the base reference frequency LO. XNOR gate 202 acts as a one-bit multiplier, and its resultant output 210 is provided to and gate 206, which performs a Boolean “and” operation on reference clock signal 200 and resultant 210. Output 213 of and gate 206 drives the clock input of N-bit counter 207, thus causing counter 207 to increment (or decrement, depending on the design) during periods of time in which reference clock signal 212 and input signal 208 have the same value. A third reference clock signal 214 at a frequency of 2LO is used to reset counter 207.
At the end of every cycle of reference clock signal 214, output 215 of counter 207 is a number that reflects the amount of phase error between input signal 208 and reference clock signal 212. Since reference clock signal 214 has a frequency of 2LO, if input signal 208 and reference clock signal 212 are perfectly in phase, counter 207 will have cycled through all 2N of its possible output values two times, and, thus, output 215 will be zero. If input signal 208 and reference clock signal 212 are not perfectly in phase, however, counter 207 will not have gone through two complete cycles of 2N output values, and output 215 will be a non-zero number. A sign detector 205 takes resultant 210, reference clock signal 214, and output 215 as inputs, and derives a signed numerical phase error 216.
For high frequency input signals, however, the Kelton et al. approach and similar counter-based designs can be somewhat impractical, however. That is because reference clock signal 200 (i.e., the clock signal that drives the counter) must be several orders of magnitude higher in frequency than the input signal, in order to have an acceptable level of accuracy. For example, if the input signal frequency is 30 MHz, a counter clock frequency of 3 GHz is needed in order to achieve +/−1% accuracy. Depending on the nature of the PLL application, such an approach may be prohibitively expensive at the frequencies of interest.
Thus, there is a need for a high-speed phase/frequency comparator design for use in phase locked loops. The present invention provides a solution to this and other problems, and offers other advantages over previous solutions.